Existing low dropout (LDO) regulator architecture uses analog voltage to control the gate drive to the LDO regulator. Generating the analog voltage may require careful design of the circuit generating the analog circuit. Generally such circuits do not scale well with process technologies. To regulate the output voltage of the LDO, head room (e.g., of about 50 mV to 120 mV) may be required between the input power supply voltage and the output voltage of the LDO regulator. With respect to the analog LDO regulator approach, there are many challenges.
For example, stability of the feedback loop of the analog LDO regulator may be extremely dependent on package parasitic and the output pole. As a result, to gain stability of the feedback loop a penalty in bandwidth may be made. The analog LDO regulator may also exhibit a minimum dropout at its output node (e.g., 50 mV to 120 mV) for LDO regulator normal operation. When input power supplies are getting lower, such minimum dropout becomes a challenge. The analog LDO regulator may also exhibit a finite direct-current (DC) offset error due to gain limitations that affect the DC set point accuracy. There are also multiple integration and design challenges in analog designs, especially those that use dual loop architecture.
A power FET (Field Effect Transistor) array may be used for an LDO regulator to provide power to the output node such that the array is connected as a parallel bank. The transfer function of this FET array is non-linear. FIG. 1A illustrates a plot 100 showing the non-linear transfer function of a parallel bank of FET array. Here, x-axis is a code. Higher the code, the more transistors in the parallel bank are turned ON. The y-axis is resistance of the parallel bank of transistors. As more transistors are turned ON (i.e., code number increases), resistance of the parallel bank falls non-linearly. Since the transfer function has a non-linear gain, for operating points of the LDO voltage regulator (VR) where the value of code ‘N’ is high, the gain of the system is low, and when the code ‘N’ is low, the gain of the system is high. This makes the transient response sharp when ‘N’ is low and sluggish when ‘N’ is high. Such non-linear response of the LDO VR is a challenge when output of the LDO VR experiences a voltage droop, for example, due to sudden change in load demand.